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 INTEGRATED CIRCUITS
DATA SHEET
SAA4993H Field and line rate converter with noise reduction
Product specification File under Integrated Circuits, IC02 2001 Nov 23
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
CONTENTS 1 2 2.1 3 4 5 6 7 8 9 10 11 FEATURES GENERAL DESCRIPTION Patent notice QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAMS PINNING FUNCTIONAL DESCRIPTION CONTROL REGISTER DESCRIPTION LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 PACKAGE OUTLINE SOLDERING
SAA4993H
Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
2001 Nov 23
2
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
1 FEATURES 2 GENERAL DESCRIPTION
SAA4993H
* Upconversion of all 1fH film and video standards up to 292 active input lines per field * 100/120 Hz 2 : 1, 50/60 Hz 1 : 1 and 100/120 Hz 1 : 1 output formats * 4 : 1 : 1, 4 : 2 : 2 and 4 : 2 : 2 Differential Pulse Code Modulation (DPCM) input colour formats; 4 : 1 : 1 and 4 : 2 : 2 output colour formats * Full 8-bit accuracy * Scalable performance by applying 2 or 3 external field memories * Improved recursive de-interlacing * Film (25 and 30 Hz) upconversion to 100/120 movement phases per second * Variable vertical sharpness enhancement * Motion compensated 3D dynamic noise reduction * High quality vertical zoom * 2 Mbaud serial interface (SNERT) * Demonstration mode for noise reduction, motion compensation and colour overlay.
The SAA4993H is a completely digital monolithic integrated circuit which can be used for field and line rate conversion of all global TV standards. It features improved Natural MotionTM(1) performance. It can be configured to emulate the SAA4990H as well as the SAA4991WP. For demonstration purposes a split screen mode to show the Dynamic Noise Reduction (DNR) function and natural motion is available, and a colour vector overlay mode exists. The SAA4993H supports a Boundary Scan Test (BST) circuit in accordance with IEEE 1149. 2.1 Patent notice
Notice is herewith given that the subject integrated circuit uses one or more of the following US patents and that each of these patents may have corresponding patents in other jurisdictions. US 4740842, US 5929919, US 6034734, US 5534946, US 5532750, US 5495300, US 5903680, US 5365280, US 5148269, US 5072293, US 5771074, and US 5302909.
(1) Natural Motion is a trademark of Koninklijke Philips Electronics N.V.
3
QUICK REFERENCE DATA SYMBOL PARAMETER core supply voltage external supply voltage (output pads) supply current operating clock frequency ambient temperature MIN. 2.3 3.0 - - 0 TYP. 2.5 3.3 280 32 - MAX. 2.7 3.6 - 33.3 70 UNIT V V mA MHz C
VDDI VDDE IDD fCLK32 Tamb 4
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME QFP160 DESCRIPTION plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height VERSION SOT322-2
SAA4993H
2001 Nov 23
3
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YB7 to YB0 151, 152, 154 to 159 45 to 52 DYNAMIC NOISE REDUCTION COMPRESS YA0 to YA7 SNCL SNDA SNRST 27 26 25 SNERT INTERFACE DE-INTERLACER CONTROL 35 34 33 32 31 30 79 UPCONVERSION BST/TEST MPR LEFT vectors MPR RIGHT VERTICAL PEAKING VERTICAL ZOOM 61 to 68 MUX MUX
5
Philips Semiconductors
FIELD MEMORY 2
DECOMPRESS SEQUENCER
handbook, full pagewidth
Field and line rate converter with noise reduction
BLOCK DIAGRAMS
FIELD MEMORY 3
YC0 to YC7 2 to 9
YD7 to YD0 111, 112, 114 to 119
YE0 to YE7 122 to 129
SAA4993H
4
TCK TDO TDI TMS TRST TE CLK32 The solid lines represent pixel data; the broken lines represent controls.
YF7 to YF0
SPM
TPM
ESM
82 to 89
YG7 to YG0
MOTION ESTIMATOR vectors
MHC054
Product specification
SAA4993H
Fig.1 Block diagram of the luminance part.
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FIELD MEMORY 2 UVB3 to UVB0 147 to 150 COMPRESS/ FORMAT UVA0 to UVA7 37 to 44 DECOMPRESS/ REFORMAT DNR
Philips Semiconductors
UVC0 to UVC3 10 to 13
DECOMPRESS/ REFORMAT
handbook, full pagewidth
Field and line rate converter with noise reduction
FIELD MEMORY 3
UVD3 to UVD0 107 to 110
UVE0 to UVE3 130 to 133
SAA4993H
5
vectors MPR LEFT UPCONVERSION VERTICAL ZOOM MPR RIGHT FORMAT 70 to 77 UVF7 to YVF0
91 to 98
UVG7 to YVG0
MHC055
Product specification
SAA4993H
The solid lines represent pixel data; the broken lines represent the data flow, if the (optional) field memory 3 is also used.
Fig.2 Block diagram of the chrominance part.
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
6 PINNING SYMBOL VSSE YC0 YC1 YC2 YC3 YC4 YC5 YC6 YC7 UVC0 UVC1 UVC2 UVC3 REC VSSE VDDE VSSI VDDI JUMP0 JUMP1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TYPE ground ground of output pads input input input input input input input input input input input input output bus C luminance input from field memory 2 bit 0 (LSB) bus C luminance input from field memory 2 bit 1 bus C luminance input from field memory 2 bit 2 bus C luminance input from field memory 2 bit 3 bus C luminance input from field memory 2 bit 4 bus C luminance input from field memory 2 bit 5 bus C luminance input from field memory 2 bit 6 bus C luminance input from field memory 2 bit 7 (MSB) bus C chrominance input from field memory 2 bit 0 (LSB) bus C chrominance input from field memory 2 bit 1 bus C chrominance input from field memory 2 bit 2 bus C chrominance input from field memory 2 bit 3 (MSB) read enable output for bus C DESCRIPTION(1)(2)
SAA4993H
ground ground of output pads supply external supply voltage (output pads) ground core ground supply core supply voltage input input configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field memory; should be connected to ground or to VDDE via a pull-up resistor of 47 k configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit 1st field memory for full 4 : 2 : 2; should be connected to ground or to VDDE via a pull-up resistor of 47 k
VDDE VDDI VSSI RAMTST1 SNRST SNDA SNCL VSSE RAMTST2 TE TRST TMS TDI
21 22 23 24 25 26 27 28 29 30 31 32 33
supply external supply voltage (output pads) supply core supply voltage ground core ground input input I/O input input input input input input test pin 1 input for internal RAM testing with internal pull-down; connect to ground for normal operation SNERT bus reset input SNERT bus data input and output SNERT bus clock input test pin 2 input for internal RAM testing with internal pull-down; connect to ground for normal operation test mode input with internal pull-down; if not used it has to be connected to ground boundary scan test reset input (active LOW); if not used it has to be connected to VDDE via a pull-up resistor of 47 k boundary scan test mode select input; if not used it has to be connected to VDDE via a pull-up resistor of 47 k boundary scan test data input; if not used it has to be connected to VDDE via a pull-up resistor of 47 k
ground ground of output pads
2001 Nov 23
6
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SYMBOL TDO TCK VSSE UVA0 UVA1 UVA2 UVA3 UVA4 UVA5 UVA6 UVA7 YA0 YA1 YA2 YA3 YA4 YA5 YA6 YA7 REA VSSE VSSI VDDI VDDI VSSI VSSE REF YF7 YF6 YF5 YF4 YF3 YF2 YF1 YF0 VDDE UVF7 UVF6 UVF5 UVF4 2001 Nov 23 PIN 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 TYPE 3-state boundary scan test data output input DESCRIPTION(1)(2)
SAA4993H
boundary scan test clock input; if not used it has to be connected to VDDE via a pull-up resistor of 47 k bus A chrominance input from field memory 1 bit 0 (LSB) bus A chrominance input from field memory 1 bit 1 bus A chrominance input from field memory 1 bit 2 bus A chrominance input from field memory 1 bit 3 bus A chrominance input from field memory 1 bit 4 bus A chrominance input from field memory 1 bit 5 bus A chrominance input from field memory 1 bit 6 bus A chrominance input from field memory 1 bit 7 (MSB) bus A luminance input from field memory 1 bit 0 (LSB) bus A luminance input from field memory 1 bit 1 bus A luminance input from field memory 1 bit 2 bus A luminance input from field memory 1 bit 3 bus A luminance input from field memory 1 bit 4 bus A luminance input from field memory 1 bit 5 bus A luminance input from field memory 1 bit 6 bus A luminance input from field memory 1 bit 7 (MSB) read enable output for bus A
ground ground of output pads input input input input input input input input input input input input input input input input output
ground ground of output pads ground core ground supply core supply voltage supply core supply voltage ground core ground ground ground of output pads input output output output output output output output output output output output output read enable input for bus F and G bus F luminance output bit 7 (MSB) bus F luminance output bit 6 bus F luminance output bit 5 bus F luminance output bit 4 bus F luminance output bit 3 bus F luminance output bit 2 bus F luminance output bit 1 bus F luminance output bit 0 (LSB) bus F chrominance output bit 7 (MSB) bus F chrominance output bit 6 bus F chrominance output bit 5 bus F chrominance output bit 4 7
supply external supply voltage (output pads)
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SYMBOL UVF3 UVF2 UVF1 UVF0 VSSE CLK32 VSSI VSSE YG7 YG6 YG5 YG4 YG3 YG2 YG1 YG0 VDDE UVG7 UVG6 UVG5 UVG4 UVG3 UVG2 UVG1 UVG0 VSSE VSSI VDDI VDDE VDDI VSSI VSSE WED UVD3 UVD2 UVD1 UVD0 YD7 YD6 VDDE YD5 2001 Nov 23 PIN 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 TYPE output output output output input bus F chrominance output bit 3 bus F chrominance output bit 2 bus F chrominance output bit 1 bus F chrominance output bit 0 (LSB) system clock input DESCRIPTION(1)(2)
SAA4993H
ground ground of output pads ground core ground ground ground of output pads 3-state bus G luminance output bit 7 (MSB) 3-state bus G luminance output bit 6 3-state bus G luminance output bit 5 3-state bus G luminance output bit 4 3-state bus G luminance output bit 3 3-state bus G luminance output bit 2 3-state bus G luminance output bit 1 3-state bus G luminance output bit 0 (LSB) supply external supply voltage (output pads) 3-state bus G chrominance output bit 7 (MSB) or vector output bit 7 3-state bus G chrominance output bit 6 or vector output bit 6 3-state bus G chrominance output bit 5 or vector output bit 5 3-state bus G chrominance output bit 4 or vector output bit 4 3-state bus G chrominance output bit 3 or vector output bit 3 3-state bus G chrominance output bit 2 or vector output bit 2 3-state bus G chrominance output bit 1 or vector output bit 1 3-state bus G chrominance output bit 0 (LSB) or vector output bit 0 ground ground of output pads ground core ground supply core supply voltage supply external supply voltage (output pads) supply core supply voltage ground core ground ground ground of output pads 3-state write enable output for bus D 3-state bus D chrominance output to field memory 3 bit 3 (MSB) 3-state bus D chrominance output to field memory 3 bit 2 3-state bus D chrominance output to field memory 3 bit 1 3-state bus D chrominance output to field memory 3 bit 0 (LSB) 3-state bus D luminance output to field memory 3 bit 7 (MSB) 3-state bus D luminance output to field memory 3 bit 6 supply external supply voltage (output pads) 3-state bus D luminance output to field memory 3 bit 5 8
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SYMBOL YD4 YD3 YD2 YD1 YD0 VSSE VSSE YE0 YE1 YE2 YE3 YE4 YE5 YE6 YE7 UVE0 UVE1 UVE2 UVE3 REE VSSE HREF VSSI VDDI OSCI RESFM VDDE VDDI VSSI ACV VSSE WEB UVB3 UVB2 UVB1 UVB0 YB7 YB6 VDDE YB5 2001 Nov 23 PIN 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 TYPE DESCRIPTION(1)(2)
SAA4993H
3-state bus D luminance output to field memory 3 bit 4 3-state bus D luminance output to field memory 3 bit 3 3-state bus D luminance output to field memory 3 bit 2 3-state bus D luminance output to field memory 3 bit 1 3-state bus D luminance output to field memory 3 bit 0 (LSB) ground ground of output pads ground ground of output pads input input input input input input input input input input input input output input bus E luminance input from field memory 3 bit 0 (LSB) bus E luminance input from field memory 3 bit 1 bus E luminance input from field memory 3 bit 2 bus E luminance input from field memory 3 bit 3 bus E luminance input from field memory 3 bit 4 bus E luminance input from field memory 3 bit 5 bus E luminance input from field memory 3 bit 6 bus E luminance input from field memory 3 bit 7 (MSB) bus E chrominance input from field memory 3 bit 0 (LSB) bus E chrominance input from field memory 3 bit 1 bus E chrominance input from field memory 3 bit 2 bus E chrominance input from field memory 3 bit 3 (MSB) read enable output for bus E horizontal reference synchronization input
ground ground of output pads ground core ground supply core supply voltage input output test pin input with internal pull-down; connect to ground for normal operation reset field memory output for pin OSCI = LOW or test output OSCOUT for pin OSCI = HIGH
supply external supply voltage (output pads) supply core supply voltage ground core ground output output output output output output output output output active video output write enable output for bus B bus B chrominance output to field memory 2 bit 3 (MSB) bus B chrominance output to field memory 2 bit 2 bus B chrominance output to field memory 2 bit 1 bus B chrominance output to field memory 2 bit 0 (LSB) bus B luminance output to field memory 2 bit 7 (MSB) bus B luminance output to field memory 2 bit 6 bus B luminance output to field memory 2 bit 5 9 ground ground of output pads
supply external supply voltage (output pads)
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SYMBOL YB4 YB3 YB2 YB1 YB0 VSSE Notes 1. Not used input pins (e.g. bus E) should be connected to ground. PIN 155 156 157 158 159 160 TYPE output output output output output DESCRIPTION(1)(2) bus B luminance output to field memory 2 bit 4 bus B luminance output to field memory 2 bit 3 bus B luminance output to field memory 2 bit 2 bus B luminance output to field memory 2 bit 1 bus B luminance output to field memory 2 bit 0 (LSB)
SAA4993H
ground ground of output pads
2. Because of the noisy characteristic of the output pad supply, it is recommended not to connect the core supply and the output pad supply directly at the device. The output pad supply should be buffered as close as possible to the device.
2001 Nov 23
10
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SAA4993H
154 YB5 153 VDDE
137 VSSI 136 HREF 135 VSSE
160 VSSE 159 YB0
146 WEB 145 VSSE
122 YE0 121 VSSE 120 VSSE 119 YD0 118 YD1 117 YD2 116 YD3 115 YD4 114 YD5 113 VDDE 112 YD6 111 YD7 110 UVD0 109 UVD1 108 UVD2 107 UVD3 106 WED 105 VSSE 104 VSSI 103 VDDI 102 VDDE 101 VDDI 100 VSSI 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VSSE UVG0 UVG1 UVG2 UVG3 UVG4 UVG5 UVG6 UVG7 VDDE YG0 YG1 YG2 YG3 YG4 YG5 YG6 YG7 VSSE 79 CLK32 VSSI 80
150 UVB0
149 UVB1
148 UVB2
147 UVB3
133 UVE3
132 UVE2
131 UVE1
130 UVE0
139 OSCI 138 VDDI
144 ACV 143 VSSI
handbook, full pagewidth
142 VDDI 141 VDDE 140 RESFM
134 REE
158 YB1
157 YB2
156 YB3
155 YB4
152 YB6
151 YB7
129 YE7
128 YE6
127 YE5
126 YE4
125 YE3 76 UVF1
124 YE2 77
VSSE YC0 YC1 YC2 YC3 YC4 YC5 YC6 YC7
1 2 3 4 5 6 7 8 9
UVC0 10 UVC1 11 UVC2 12 UVC3 13 REC 14 VSSE 15 VDDE 16 VSSI 17 VDDI 18 JUMP0 19 JUMP1 VDDE 20 21
SAA4993H
VDDI 22 VSSI 23 RAMTST1 SNRST SNDA SNCL VSSE RAMTST2 TE TRST TMS TDI TDO TCK VSSE UVA0 UVA1 UVA2 UVA3 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 YA5 50 YA6 51 YA7 52 REA 53 VSSE 54 VSSI 55 VDDI 56 VDDI 57 VSSI 58 VSSE 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 78
YF7
YF6
YF5
YF4
YF3
YF2
YF1
YF0
UVF7
UVF6
UVF5
UVF4
UVF3
UVF2
VDDE
UVF0 VSSE
UVA4
UVA5
UVA6
UVA7
YA0
YA1
YA2
YA3
YA4
REF
123 YE1
MHC056
Fig.3 Pin configuration.
2001 Nov 23
11
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
7 FUNCTIONAL DESCRIPTION Table 1 Clock cycle references
SAA4993H
The fal_top module builds the functional top level of the SAA4993H. It connects the luminance data path, the chrominance data path and the luminance (de)compression with SAA4993H inputs and outputs as well as controlling logic. Outside of the fal_top module, there are only the pad cells, boundary scan test cells, the boundary scan test controller, the clock tree, the test enable tree and the input port registers. Figure 4 shows a simplified block diagram of the fal_top module. It displays the flow of pixel data (solid lines) and controls (broken lines) between the modules inside. Basic functionality of the modules in the fal_top module is as follows: * KER (kernel): Y (luminance) data path * COL (colour): UV (chrominance) data path * YDP (Y-DPCM): compression (and decompression) of luminance output (and input) data by Differential Pulse Code Modulation (DPCM) * LSE (line sequencer): generate line frequent control signals * SNE (interface): Synchronous No parity Eight bit Reception and Transmission (SNERT) interface to a microcontroller. The SNERT interface operates in a slave receive and transmit mode for communication with a microcontroller, which resides on peripheral circuits (e.g. SAA4978H) together with a SNERT master. The SNERT interface transforms serial data from the microcontroller (via the SNERT bus) into parallel data to be written into the SAA4993Hs write registers and parallel data from SAA4993Hs read registers into serial data to be sent to the microcontroller. The SNERT bus consists of 3 signals: 1. SNCL: used as serial clock signal, generated by the master 2. SNDA: used as bidirectional data line 3. SNRST: used as a reset signal, generated by the microcontroller to indicate the start of a transmission. The processing of a video field begins on the rising edge of the RE_F input signal. As indicated in Fig.4, the SAA4993H receives its inputs and generates its outputs at the following clock cycles after RE_F (see Table 1).
SIGNAL RE_F RE_C and RE_E YC, YE, UVC and UVE RE_A YA and UVA YF, YG, UVF and UVG WE_B and WE_D YB, YD, UVB and UVD 0
LATENCY 62 cycles + REceShift 63 cycles 93 cycles + REaShift 94 cycles 147 cycles + 3 input lines 159 cycles + 4 input lines + WEbdShift 159 cycles + 4 input lines
There is an algorithmic delay of 3 lines between input and output data. Therefore, the main data output on the F and G bus begins while the fourth input line is read. Writing to the B and D bus starts one input line later. The read and write enable signals RE_A, WE_B, RE_C, WE_D and RE_E can be shifted by control registers REaShift, WEbdShift and REceShift, which are implemented in the line sequencer. The fal_top module itself reads the following control register bits (addresses): * NrofFMs (017H) * MatrixOn (026H) and BusGControl (028H) * MemComp and MemDecom (026H). NrofFMs, MatrixOn and BusGControl are used to enable the D and G output bus, respectively. MemComp and MemDecom are connected to YDP to control luminance data compression and decompression. These control register signals are not displayed in Fig.4. Further information on the control registers is given in Chapter 8.
2001 Nov 23
12
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SAA4993H
handbook, full pagewidth
external field memories WE_B, WE_D RE_C, RE_E 62 cycles UVB, UVD 159 cycles UVC, UVE 63 cycles YB, YD 159 cycles YC, YE 63 cycles
fal_top
UVA 94 cycles
159 cycles
YDP COL UVF, UVG 147 cycles
SNDA RE_A 93 cycles
SNE
LSE RE_F 0 cycles YF, YG 147 cycles
YA 94 cycles
KER
MHC057
The solid lines represent pixel data; the broken lines represent controls.
Fig.4 Block diagram of fal_top.
2001 Nov 23
13
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Field and line rate converter with noise reduction
NAME DNR/peaking/colour Kstep10 Kstep0 Kstep1 Kstep32 Kstep2 Kstep3 Kstep54 Kstep4 Kstep5 Kstep76 Kstep6 Kstep7 Gain_fix_y FixvalY GainY FixY Gain_fix_uv FixvalUV GainUV FixUV Peak_Vcomp VecComp PeakCoef
SNERT READ/ ADDRESS 76543210 WRITE(1) (HEX)
DESCRIPTION(2)
010
write; S X X X X set LUT value: k = 116 if difference below (0 to 15) XXXX set LUT value: k = 18 if difference below (0 to 15) X X X X set LUT value: k = 28 if difference below (0 to 30 in multiples of 2) XXXX set LUT value: k = 38 if difference below (0 to 30 in multiples of 2) X X X X set LUT value: k = 48 if difference below (0 to 60 in multiples of 4) XXXX set LUT value: k = 58 if difference below (0 to 60 in multiples of 4) X X X X set LUT value: k = 68 if difference below (0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112 or 120) XXXX set LUT value: k = 78 if difference below (0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112 or 120) X X X X set fixed Y value; used when FixY = 1 or in left part of split screen (0, 116 to 1416 or 1616) XXX X set gain in difference signal for adaptive DNR Y (18, 14, 12, 1, 2 or 4) select fixed Y (adaptive or fixed) (full screen) X X X X set fixed UV value; used when FixUV = 1 or in left part of split screen (0, 116 to 1416 or 1616) XXX X set gain in difference signal for adaptive DNR UV (18, 14, 12, 1, 2 or 4) select fixed UV (adaptive or fixed) (full screen)
011
write; S
012
write; S
013
write; S
014
write; S
015
write; S
Product specification
SAA4993H
016
write; S X X X set degree of horizontal vector compensation in Y DNR: (0, 18, 28, 38, 48, 58, 68 or 78) of the vector XXXX set vertical peaking level: (0, +2, +3.5, +5, +6, x, x, x, x, x, x, x, x, -12, -6 or -2.5) dB
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Field and line rate converter with noise reduction
NAME DNR_Colour_mode ColourIn ColourOut NrofFMs ColOvl SlaveUVtoY DnrSplit DnrHpon Vertical zoom Zoom1 ZoomSt98
DESCRIPTION(2)
018
write; F X X zoom line step bits 9 and 8; line step = vertical distance between successive output lines; usable range = 0 to 2 frame lines; resolution 1256 frame line zoom start position bits 9 and 8; start position = vertical position of the top display line; usable range = 1 to 3 frame lines; resolution 1256 frame line
SAA4993H
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Field and line rate converter with noise reduction
NAME De-interlacer Proscan1 KlfLim KlfOfs
DESCRIPTION(2)
01C
write; S X X X X limitation of recursion factor in calculation of original line positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no recursion XXXX The transfer curve of the de-interlacing filter coefficient is determined by the difference (Diff) between a line in the input field and the counterpart in the previous field shifted over the estimated motion vector. KlfOfs determines the bias of the transfer curve for the original input line, such that coefficient = KlfOfs + F(Diff), where the function F is calculated in the SAA4993H. The bias can take a value in the range (0 to 15), representing decreasing filter strength. X X X X limitation of recursion factor in calculation of interpolated line positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no recursion XXXX see KlfOfs; this offset applies to interpolated lines X X X X Maximum that the peaked pixel is allowed to deviate from original pixel value: deviation (0 to 30 in steps of 2). Above this deviation, the peaked pixel is clipped to (original pixel + or - PeakLim). XXXX offset to bias between average and median in the initial de-interlacing, if the KplFad = MIX option is chosen
Proscan2 PlfLim
01D
write; S
PlfOfs Proscan3 PeakLim 01E write; S
DeiOfs
Product specification
SAA4993H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Nov 23 17 Philips Semiconductors SNERT READ/ ADDRESS 76543210 WRITE(1) (HEX) 01F write; F X X X Multiplier threshold at which to switch the lower limit of the filter coefficient for interpolated lines. Above this threshold, the differences corresponding to the two neighbouring lines are used as clipping parameters, below this threshold, the interpolated line difference is used as clipping level. This parameter can be used to optimize the de-interlacing quality in slowly moving edges; it is not likely to have effect if PlfLim is high. X XX select adaptive recursive or order statistic output (order statistic or adaptive) Scaling factor to control the strength of the filtering for the interpolated lines. A value 0 means no scaling (normal filtering), while 3 means scaling by factor 8 (very strong filtering). This parameter can be used to adjust the de-interlacing to varying level of noise in the input picture; use higher scaling for higher noise. disable all recursion in calculating pixels for frame memory (recursive or non recursive); to be true SAA4991WP and digital scan emulation modes X X X X Roll back factor on vectors used for motion-compensated de-interlacing. Values 0 to 14 (on a scale of 16) indicate attenuation. A value of 15 indicates no attenuation. XXX X sensitivity scaling factor in transition from average to median in initial de-interlacing chooses between majority selection and median/average mix for initial de-interlacing (majority or mix); when KplFad = 0, FadDiv and DeiOfs are don't cares
Field and line rate converter with noise reduction
NAME Proscan4 PlfThr
DESCRIPTION(2)
AdRecOut ProDiv
KplOff
X
Proscan5 VecRbf
0CB
write; S
FadDiv KplFad
Product specification
SAA4993H
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Field and line rate converter with noise reduction
NAME General NrBlks NrBlks
DESCRIPTION(2)
020
write; S X X X X X X number of blocks in active video (6 to 53, corresponds to 96 to 848 pixels), to be set as 116 (number of active pixels per line + 15); take remarks on TotalPxDiv8 into consideration XX total number of output lines (bits 9 and 8)
TotalLnsAct98 TotalLnsAct70 TotalPxDiv8 021 022 write; S write; S
X X X X X X X X total number of output lines (bits 7 to 0) X X X X X X X X Total number of pixels per line divided-by-8 (80 to 128, corresponds to 640 to 1024 pixels). The horizontal blanking interval is calculated as TotalPxDiv8 - 2 x NrBlks and has to be in the range from 12 to 124 (corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be set to 12 + 2 x NrBlks < TotalPxDiv8 < 124 + 2 x NrBlks and NrBlks TotalPxDiv8 - 124 TotalPxDiv8 - 12 has to be set to ----------------------------------------------- < NrBlks < -------------------------------------------2 2 X X X shift of RE_A signal in number of pixels (0, +1, +2, +3, -4, -3, -2 or -1) X X X shift of WE_B and WE_D signal in number of pixels (0, +1, +2, +3, -4, -3, -2 or -1) XXX shift of RE_C and RE_E signal in number of pixels (0, +1, +2, +3, -4, -3, -2 or -1) X power-on reset command, to be set high temporarily during start-up (normal or reset); note 3 X X X X X X X X 8-bit scaling factor for EggSliceMix, EggSliceRgt and global activity (the same factor for all registers). ScalingFactor output value (n+1) = ----------------------------------- x output value (n) 128
REaShift WEbdREceShift WEbdShift REceShift POR ScalingFactor
023 024
write; S write; S
025 0D6
write; S write; S
Product specification
SAA4993H
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Field and line rate converter with noise reduction
NAME Mode control Control1 EstMode
DESCRIPTION(2)
026
write; F X Set estimator mode; 0 = line alternating use of left and right estimator: use in progressive scan except with vertical compress. 1 = field alternating use of left and right estimator: use in field doubling and progressive scan with vertical compress. X XX X set film mode; 0 = video camera mode; 1 = film mode select upconversion quality; 00 = full, 01 = economy (DPCM), 10 = SAA4991WP, 11 = SAA4990H set matrix output mode; 1 = double output, disabling vertical peaking; 0 = normal single output mode; this bit setting is the AND function of BusGControl bits Master enable for embrace mode (off or on); SwapMpr in control2 should be at `swap' position to really cross-switch FM1 and FM3 field outputs. Should be set to logic 0 except in film mode and FM3 is present, or in SAA4991WP film mode and MemComp bit is active. set memory compression (luminance DPCM) (off or on) set memory decompression (luminance DPCM) (off or on)
FilmMode UpcMode MatrixOn
EmbraceOn
X
Product specification
SAA4993H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Nov 23 20 Philips Semiconductors SNERT READ/ ADDRESS 76543210 WRITE(1) (HEX) 027 write; F X Quincunx phase of current field (in TPM) (phase0 or phase1); this needs to toggle each time a new field comes from FM1. In phase0 the estimator operates on a checker-board pattern that starts with the left upper block; in phase1 the other blocks are estimated. X quincunx phase of previous field (in TPM) (phase0 or phase1); this is the value of QQcur during the last estimate written into the temporal prediction memory Field status (same input field or new input field); reflects whether the output of FM1 is a new or a repeated field. This bit will toggle field by field in field doubling mode and is continuously HIGH in progressive output mode. enable writing FM2 and FM3 for both luminance and chrominance (recirculation of data for luminance alone can be controlled with OrigFmEnY and IntpFmEnY in Control3) (off or on) odd input field (even or odd), this is to be set equal to the detected field interlace for the field that comes out of FM1 Swap multi port RAMs (normal or swap); this bit needs to be set to get real frame data at the temporal position from FM1. If swapped, the current field (FM1) will be stored in the right line memory tree, while the original lines from the stored frame (FM2/3) are stored in the left memory tree. Should be set only in film mode if FM3 is present; EmbraceOn must be set as well. Set vertical vector offset (0, +1, - or -1) frame lines; vertical offset of the right line memory tree with respect to the left line memory tree. A higher offset value means: on the right memory tree access to less delayed video lines is taken; in interlaced video operation, the vertical offset will be -1 with an odd field on the left side and +1 with an even field on the left. With non-interlaced input, vertical offset should be constantly 0. In film mode, vertical offset is dynamically switched between +1, 0 and -1.
Field and line rate converter with noise reduction
NAME Control2 QQcurr
DESCRIPTION(2)
QQprev
FldStat
X
FieldWeYUV
X
OddFM1 SwapMpr X
X
VecOffs
XX
Product specification
SAA4993H
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Field and line rate converter with noise reduction
NAME Control3 OddLeft OrigFmEnY
DESCRIPTION(2)
IntpFmEnY
X
FillTPM
X
VertOffsDNR
XX
SAA4993H
X X X X X X temporal interpolation factor used in luminance upconverter; value ranges from 0 (for current field position) to 32 (for previous field position)
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Field and line rate converter with noise reduction
NAME Upconv2 YVecClip
DESCRIPTION(2)
RollBack Upconv3 MelzLfbm Melzmemc 02B
F write; S
MelDeint
X
MixCtrl
XXXXX
UpcColShiFac
0C4
write; F
X X X X X X temporal interpolation factor used in chrominance upconverter; value ranges from 0 (for current field position) to 32 (for previous field position) X X X Number of consecutive lines to have bad egg-slice values before upconverter goes into protection mode (0, 1, 2, 4, 8, 16, 32 or 64). A value of 0 switches off the possibility to go into protection. X mode switch on left side of the screen; 0 (natural motion); 1 (digital scan-like processing) Product specification
Upconv4 LfIndex
0C5
write; S
MCDemo EggSlice1 EggStartLine 0C6 write; S
SAA4993H
X X X X X X X X Reference line number at which the egg slice measurement should start. SAA4993H defines a window internally as number of lines between EggStartLine and (MaxRefLine - EggStartLine).
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Nov 23 23 BmsThr XX Motest2 TavLow 02D write; S X If the difference between the current vector and the previous one in the same spatial location is within a small window, then the two vectors are averaged to improve temporal consistency. TavLow is the lower threshold of this window (1 or 2). XX XX XX see above; TavUpp is the upper threshold (0, 4, 8 or 16) scaling factor to reduce all sizes of update vectors in the ensemble with medium sized vector templates (1, 12, 14 or 18) scaling factor to reduce all sizes of update vectors in the ensemble with large sized vector templates (1, 12, 14 or 18) Product specification TavUpp MedEns LarEns Philips Semiconductors SNERT READ/ ADDRESS 76543210 WRITE(1) (HEX) 0C7 write; S X X X X X X Minimum line egg slice right value to activate reliability measurement. The parameter is multiplied internally by 4. XX the egg slice reliability is computed internally as EggSliceRgt (ESR) > RelFactor x EggSliceMix (ESM). RelFactor is determined by EggRelInd (28, 38, 48, or 68). X X X X X X upconverter shift factor to be used in protection mode; 0 (for current field position) to 32 (for previous field position)
Field and line rate converter with noise reduction
NAME EggSlice2 EggSlcThr EggRelInd
DESCRIPTION(2)
SafeShiFac Motion estimator Motest1 PenOdd SpcThr
0C8
write; F
02C
write; S X X X additional penalty on vector candidates with odd vertical component (0, 8, 16, 32, 64, 128, 256 or 511) XXX Active when EstMode = 0; replace the spatial prediction of one estimator (left or right) by that of the other if the match error of the former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128, 256 or 511). A higher threshold means the two estimators are very independent. Active when EstMode = 0; select as estimated vector the output of the right estimator unless its match error exceeds that of the left estimator by more than (0, 8, 16 or 32). This parameter should normally be set to logic 0.
SAA4993H
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Field and line rate converter with noise reduction
NAME Motest3 MotShiFac
DESCRIPTION(2)
Motest4 PenRng
Product specification
SAA4993H
write zeros in the temporal prediction memory (no writing or writing zeros)
X X X X X X X X blocks having an activity value below or equal to this threshold are counted as having LOW activity X X X X X X X X blocks having an activity value above this threshold are counted as having HIGH activity
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Field and line rate converter with noise reduction
NAME LeftBorder LeftBorder WinNullWrite RightBorder TopBorder BottomBorder Candidate1 Candidat1 Update1 Penalty1 Candidate2 Candidat2 Update2 Penalty2 Candidate3 Candidat3 Update3 Penalty3 Candidate4 Candidat4 Update4 Penalty4
DESCRIPTION(2)
SAA4993H
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Field and line rate converter with noise reduction
NAME Candidate5 Candidat5 Update5 Penalty5 Candidate6 Candidat6 Update6 Penalty6 Candidate7 Candidat7 Update7 Penalty7 Candidate8 Candidat8 Update8 Penalty8 PZpositionLeftUppX PZpositionLeftUppY
DESCRIPTION(2)
X X X X X X X position of LeftUpp measurement point for pan-zoom calculations (resolution: 16 pixels) X X X X X X X Y position of LeftUpp measurement point for pan-zoom calculations (resolution: 4 lines) X X X X X X X position of RightLow measurement point for pan-zoom calculations (resolution: 16 pixels) X X X X X X X Y position of RightLow measurement point for pan-zoom calculations (resolution: 4 lines) X X X X X X X X X start value of pan-zoom vectors Product specification
SAA4993H
PZpositionRightLowX 09A PZpositionRightLowY 09B PZvectorStartX 09C
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Field and line rate converter with noise reduction
NAME PZvectorDeltaX PZvectorStartY PZvectorDeltaY Read data; note 3 GlobalMSEmsb GlobalMSElsb
DESCRIPTION(2)
X X X X X X X X X delta value of pan-zoom vectors X X X X X X X X Y start value of pan-zoom vectors X X X X X X X X Y delta value of pan-zoom vectors
0A0 0A1
read; F read; F
X X X X X X X X Global Mean Square Error (MSE) = summation within a field period of X X X X X X X X squared differences in comparing vector shifted video from frame memory (FM2/3) with new field input (FM1) in those lines coinciding with new field lines. The window for the measurement is kept at 40 pixels horizontal and 20 field lines vertical from the border of the video. Measurements is only done in fields where the de-interlacer is active, otherwise reading is zero. In field doubling mode, MSE is zero at the end of every new input field. X X X X X X X X Global Motion Trajectory Inconsistency (MTI) = summation within a X X X X X X X X field period of squared differences comparing shifted video from frame memory (FM2/3 output) with filtered data that is rewritten to the frame memory (FM2/3 input) in those lines coinciding with new field lines. The window for the measurement is kept at 40 pixels horizontal and 20 field lines vertical from the border of the video. Measurement is done only in fields where de-interlacer is active, otherwise reading is zero; in field doubling mode, MTI is zero at the end of every new input field. X X X X X X X X global activity (ACT) = summation over a field period of the horizontal X X X X X X X X plus the vertical components of the vectors of all blocks X X X X X X X X Vector temporal consistency = summation over a field period of absolute differences of horizontal plus vertical components of vectors newly estimated for each block compared with those vectors estimated in the previous run at the same spatial block position. It should be noted that a lower figure implies better consistency. X X X X X X X X Vector spatial consistency = summation over a field period of absolute differences of horizontal and vertical components of vectors compared with those of the neighbour blocks (L, R, U and D); in the comparison, all vector data is used from the previous estimator run. It should be noted that a lower figure implies better consistency. X X X X X X X X burst error count (number of burst errors)
GlobalMTImsb GlobalMTIlsb
0A2 0A3
read; F read; F
Product specification
SAA4993H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Nov 23 28 PanZoomVec0-X PanZoomVec0-Y FalconIdent PanZoomVec0-Y PanZoomVec1-X PanZoomVec1-Y StatusJump0 PanZoomVec1-Y PanZoomVec2-X PanZoomVec2-Y StatusJump1 PanZoomVec2-Y PanZoomVec3-X PanZoomVec3-Y 0B6 0B7 0B4 0B5 0B2 0B3 0B0 0B1 read; F read S F read; F read S F read; F read S F read; F read; F X read out of configuration pin JUMP1 X X X X X X X pan-zoom vector 2 (7-bit Y value) X X X X X X X X pan-zoom vector 2 (8-bit X value) X X X X X X X pan-zoom vector 3 (7-bit Y value) X read out of configuration pin JUMP0 X X X X X X X pan-zoom vector 1 (7-bit Y value) X X X X X X X X pan-zoom vector 2 (8-bit X value) Product specification 0 SAA4993H identification: fixed bit, reading this bit as zero means SAA4993H is present X X X X X X X pan-zoom vector 0 (7-bit Y value) X X X X X X X X pan-zoom vector 1 (8-bit X value) Philips Semiconductors SNERT READ/ ADDRESS 76543210 WRITE(1) (HEX) 0A9 read; F
Field and line rate converter with noise reduction
NAME LeastErrSum
DESCRIPTION(2)
X X X X X X X X least error sum (summation over a field period of the smallest match error that the estimator has found for each block: indicates reliability of the estimation process) X X X X X X X X Y vector range error count (number of vectors that have a vertical component that is out of range for upconversion at the chosen temporal position) (15 to 8) X X X X X X X X Y vector range error count (7 to 0) X X X X X X X X read out of (number of input (run-) lines - 40) used in previous field X X X X X X X X Write of [number of input (run-) lines - 40] to be used in new field (actual maximum number of input lines in normal operation: 292; register value 252). Nominally this is to be set as an exact copy of the value read from RefLineCountPrev before a new field starts. In case the effective number of input (run-) lines has increased, RefLineCountNew should, for one field, be set to 255. This will occur e.g. with decreasing vertical zoom magnification or changing from 525 lines video standard to 625 lines standard. If this is not done, a deadlock will occur with too few lines processed correctly by the motion estimator. X X X X X X X X pan-zoom vector 0 (8-bit X value)
YvecRangeErrCntmsb 0AA
read; F
YvecRangeErrCntlsb RefLineCountPrev RefLineCountNew
0AB 0AC 0AD
read; F read; F write; F
SAA4993H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Nov 23 29 Philips Semiconductors SNERT READ/ ADDRESS 76543210 WRITE(1) (HEX) 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF 0AE 0AF 0C0 0C1 0C2 0C3 0C9 0CA read; F read; F read; F read; F read; F read; F read; F read; F read; F read; F read; F read; F read; F read; F read; F read; F
Field and line rate converter with noise reduction
NAME PanZoomVec4-X PanZoomVec4-Y PanZoomVec5-X PanZoomVec5-Y PanZoomVec6-X PanZoomVec6-Y PanZoomVec7-X PanZoomVec7-Y PanZoomVec8-X PanZoomVec8-Y EggSliceRgtMSB EggSliceRgtLSB EggSliceMixMSB EggSliceMixLSB SafeFbLine EggBinGoodness
DESCRIPTION(2)
X X X X X X X X pan-zoom vector 4 (8-bit X value) X X X X X X X pan-zoom vector 4 (7-bit Y value) X X X X X X X X pan-zoom vector 5 (8-bit X value) X X X X X X X pan-zoom vector 5 (7-bit Y value) X X X X X X X X pan-zoom vector 6 (8-bit X value) X X X X X X X pan-zoom vector 6 (7-bit Y value) X X X X X X X X pan-zoom vector 7 (8-bit X value) X X X X X X X pan-zoom vector 7 (7-bit Y value) X X X X X X X X pan-zoom vector 8 (8-bit X value) X X X X X X X pan-zoom vector 8 (7-bit Y value) X X X X X X X X result of right pixels egg-slice detector (15 to 8) X X X X X X X X result of right pixels egg-slice detector (7 to 0) X X X X X X X X result of mixed pixels egg-slice detector (15 to 8) X X X X X X X X result of mixed pixels egg-slice detector (7 to 0) X X X X X X X X reference line number (divided by two) at which the upconverter goes into protection mode X X X X X X X X Goodness of the four egg-slice sections, from top to bottom, 2 bits per section. Each section is represented with 2 bits in this register, where bits 0 and 1 represent the top section and bits 6 and 7 represent the lowest of the 4 sections. Each pair of bits indicate 00 = (ESR > 34ESM), 01 = (12ESM < ESR 34ESM), 10 = (14ESM < ESR 12ESM), 11 = (ESR 14ESM). X X X X X X X X number of blocks having low activity X X X X X X X X number of blocks having high activity X X X X X X X X sum of errors for the null candidate over the complete field; when no null candidate is selected a value of 0xFF will be read
LoActCnt HiActCnt NullErrSum
0D3 0D4 0D5
read; F read; F read; F
Product specification
SAA4993H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Notes 2001 Nov 23 30 Product specification Philips Semiconductors
Field and line rate converter with noise reduction
1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each display field. 2. Selectable items are marked bold. 3. Almost all of the R(ead) and W(rite) registers of SAA4993H are double buffered. The Write registers are latched by a signal called New_field. New_field gets set, when RE_F rises after RSTR (New_field is effectively at the start of active video). The Read registers are latched by a signal called Reg_upd. Reg_upd gets set, when half the number of active pixels of the fourth line of vertical blanking have entered the SAA4993H (Reg_upd will effectively be active 312 lines after the RE_A, RE_C and RE_E have ended). The only exception are the registers which are not double buffered, these are as follows: a) Write register 025H: power_on_reset b) Write register 02FH, bit 1: CndSet c) Read register 0B0H to 0BFH, 0AEH and 0AFH: pan_zoom_vectors, including FalconIdent (= 0), StatusJump0 and StatusJump1.
SAA4993H
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDI VDDE IDD Io Vi Tstg Tj PARAMETER core supply voltage external supply voltage (output pads) supply current output current input voltage for all I/O pins storage temperature junction temperature -0.5 -0.5 - - -0.5 -40 0 MIN. +2.7 +3.6 600 4 +3.6 +125 125 MAX.
SAA4993H
UNIT V V mA mA V C C
10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Rth(j-c) PARAMETER thermal resistance from junction to case CONDITIONS VALUE 27 2.9 UNIT K/W K/W
thermal resistance from junction to ambient in free air
11 CHARACTERISTICS VDDE = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supplies VDDI VDDE IDD General VOH VOL VIH VIL IOH HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current 10 ns slew rate output; VOH = 2.4 V 10 ns slew rate output; VOL = 0.4 V 2.4 - 2 - -4 - - - - - - 0.4 - 0.8 - V V V V mA core supply voltage external supply voltage (output pads) supply current 2.3 3.0 - 2.5 3.3 280 2.7 3.6 - V V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IOL
LOW-level output current
4
-
-
mA
CL Ci ILI
load capacitance input capacitance input leakage current
- - -
- - -
50 8 1
pF pF A
2001 Nov 23
31
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SYMBOL Outputs; see Fig.5; note 1 IOZ td(o) th(o) SR output current in 3-state mode output delay time (except pin RESFM) output hold time (except pin RESFM) slew rate -0.5 < Vo < 3.6 - - 4 300 - - - - - - - - - - 1 - - - - - - - - - - - - PARAMETER CONDITIONS MIN. TYP.
SAA4993H
MAX.
UNIT A ns ns mV/ns
1 21 - 700 - - 4 4 60 39 - - - - 30 - - 1 - - - 330 -
Inputs; see Fig.5; note 2 tsu(i) th(i) tr tf Tcy Tcy(BST) tsu(i)(BST) th(i)(BST) th(o)(BST) td(o)(BST) tSNRST(H) td(SNRST-SNCL) Tcy(SNCL) tsu(i)(SNCL) th(i)(SNCL) th(o) td(o) to(en) Notes 1. Timing characteristics are measured with CL = 15 pF; IOL = 2 mA; RL = 2 k. 2. All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs. input set-up time input hold time 6 2 - - 40 30 - 3 6 4 - 500 200 0.5 53 10 30 - 210 ns ns
Input CLK32; see Fig.5 rise time fall time duty factor cycle time ns ns % ns s ns ns ns ns
BST interface; see Fig.6 BST cycle time input set-up time input hold time output hold time output delay
SNERT interface; see Fig.7 SNRST pulse HIGH time delay SNRST pulse to SNCL LOW time SNCL cycle time input set-up time to SNCL input hold time to SNCL output hold time output delay output enable time ns ns s ns ns ns ns ns
2001 Nov 23
32
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SAA4993H
handbook, full pagewidth
tf 90%
tr 90% 1.5 V 10%
CLOCK 10%
INPUT DATA
MHB175
tsu(i)
th(i)
OUTPUT DATA
data valid th(o)
data transition period
td(o)
Fig.5 Data input/output timing diagram.
handbook, full pagewidth
Tcy(BST)
TCK
TDI, TMS t su(i)(BST) t h(i)(BST)
MHB649
TDO t h(o)(BST) t d(o)(BST)
Fig.6 Boundary scan test interface timing diagram.
2001 Nov 23
33
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
SAA4993H
handbook, full pagewidth
SNCL
write sequence: SNDA read sequence: SNDA driven by master SNDA driven by SAA4993H a0 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 w0 w1 w2 w3 w4 w5 w6 w7
r0
r1
r2
r3
r4
r5
r6
r7
SNCL t su(i)(SNCL) write sequence: SNDA read sequence: SNDA driven by master SNDA driven by SAA4993H a6
50% t h(i)(SNCL) a7
50%
50%
w0
w1
a6
a7 t o(en) r0 t d(o) t d(o) t h(o) r1
MHC058
Fig.7 SNERT interface timing diagram.
2001 Nov 23
34
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
Table 2 YUV formats FORMAT(2) 4:1:1 YX7 YX6 YX5 YX4 YX3 YX2 YX1 YX0 UVX7 UVX6 UVX5 UVX4 UVX3 UVX2 UVX1 UVX0 Notes 1. Digit X refers to different I/O buses: a) A = input from 1st field memory b) B = output to 2nd field memory c) C = input from 2nd field memory d) D = output to 3rd field memory e) E = input from 3rd field memory f) F = main output g) G = 2nd output for matrix purposes. 2. The first index digit defines the sample number and the second defines the bit number. Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 - - - - Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 - - - - Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 - - - - Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 - - - - Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 4:2:2 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00
SAA4993H
I/O PIN(1)
4 : 2 : 2 DPCM Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 UC03 UC02 UC01 UC00 - - - - Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 VC03 VC02 VC01 VC00 - - - -
2001 Nov 23
35
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
12 PACKAGE OUTLINE QFP160: plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height
SAA4993H
SOT322-2
c
y
X
A 120 121 81 80 ZE
e E HE A A2 A1 (A 3) Lp L detail X 41 1 bp D HD wM ZD B vM B 40 vM A
wM bp pin 1 index 160
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT322-2 REFERENCES IEC 135E12 JEDEC MS-022 EIAJ EUROPEAN PROJECTION A max. 4.07 A1 0.50 0.25 A2 3.60 3.20 A3 0.25 bp 0.38 0.22 c 0.23 0.13 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.65 HD HE L 1.6 Lp 1.03 0.73 v 0.3 w 0.13 y 0.1 Z D(1) Z E (1) 1.5 1.1 1.5 1.1 7 0o
o
31.45 31.45 30.95 30.95
ISSUE DATE 99-11-03 00-01-19
2001 Nov 23
36
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
13 SOLDERING 13.1 Introduction to soldering surface mount packages
SAA4993H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2001 Nov 23
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
13.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SAA4993H
SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2001 Nov 23
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction
14 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
SAA4993H
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 15 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips 2001 Nov 23 39 Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ICs with field conversion functionality Purchase of a Philips IC with field conversion functionality does not convey any implied license under any Intellectual Property Right to use this IC in any field conversion application, such as but not limited to a TV set having a display with a 100 Hz field refresh rate. A license can be obtained via the Philips Corporate Intellectual Property department. For more information, please contact Philips Corporate Intellectual Property, Attn. Patent Licensing Manager, P.O. Box 220, 5600 AE Eindhoven, The Netherlands, email: licensing.cip@philips.com.
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp40
Date of release: 2001
Nov 23
Document order number:
9397 750 08704


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